`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/23/2024 13:42:08 PM
// Design Name: 
// Module Name: axi_nr_mib_recovery
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module axi_gt_common_sdm #
(  
    parameter ADDR_WIDTH        = 32,
    parameter DATA_WIDTH        = 32,
    parameter ADDRESS_WIDTH     = 12
)  
(
    input           fbclk               ,
    input           sys_clk             ,
    input           gtrefclk00          ,
    input           gtrefclk01          ,
    input           qpll0reset          ,

    output [ 0:0]   txn_out             ,
    output [ 0:0]   txp_out             ,
    output          qpll0lock_out       ,
    output          qpll0outclk_out     ,
    output          qpll0outrefclk_out  ,
    output          rxoutclk_out        ,
    output          txoutclk_out        ,

    // axi interface lite
    (* x_interface_info = "xilinx.com:signal:clock:1.0 lite_clk CLK" *) 
    (* x_interface_mode = "slave lite_clk" *) 
    (* x_interface_parameter = "XIL_INTERFACENAME lite_clk, ASSOCIATED_BUSIF AXI_LITE, ASSOCIATED_RESET s_axi_aresetn" *) 
    input                           s_axi_aclk          ,
    (* x_interface_info = "xilinx.com:signal:reset:1.0 lite_reset RST" *)
    (* x_interface_mode = "slave lite_reset" *) 
    (* x_interface_parameter = "XIL_INTERFACENAME lite_reset, POLARITY ACTIVE_LOW" *) 
    input                           s_axi_aresetn       ,

    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR" *) 
    (* x_interface_mode = "slave AXI_LITE" *) 
    (* x_interface_parameter = "XIL_INTERFACENAME AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, ADDR_WIDTH 32" *) 
    input      [ADDR_WIDTH-1:0]     s_axi_awaddr        ,
    // AXI Write Address Channel
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID" *) 
    input                           s_axi_awvalid       ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE AWPROT" *) 
    input      [  2  :  0     ]     s_axi_awprot        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY" *) 
    output                          s_axi_awready       ,
    // AXI Write Data Channel
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID" *) 
    input                           s_axi_wvalid        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA" *) 
    input      [DATA_WIDTH-1:0]     s_axi_wdata         ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB" *) 
    input      [  3  :  0     ]     s_axi_wstrb         ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY" *) 
    output                          s_axi_wready        ,
    // AXI Write Response Channel
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID" *) 
    output                          s_axi_bvalid        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP" *) 
    output     [  1  :  0     ]     s_axi_bresp         ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY" *) 
    input                           s_axi_bready        ,
    // AXI Read Address Channel
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID" *) 
    input                           s_axi_arvalid       ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR" *) 
    input      [ADDR_WIDTH-1:0]     s_axi_araddr        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE ARPROT" *) 
    input      [  2  :  0     ]     s_axi_arprot        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY" *) 
    output                          s_axi_arready       ,
    // AXI Read Data Channel
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID" *)
    output                          s_axi_rvalid        ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA" *) 
    output     [DATA_WIDTH-1:0]     s_axi_rdata         ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP" *) 
    output     [  1  :  0     ]     s_axi_rresp         ,
    (* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY" *)
    input                           s_axi_rready
);

  
    // AXI to registers and bus interface
    wire                      up_wreq     ;
    wire [ADDRESS_WIDTH-1:0]  up_waddr    ;
    wire [DATA_WIDTH-1:0]     up_wdata    ;
    wire                      up_wack     ;
    wire                      up_rreq     ;
    wire [ADDRESS_WIDTH-1:0]  up_raddr    ;
    wire [DATA_WIDTH-1:0]     up_rdata    ;
    wire                      up_rack     ; 

    wire [24:0]               sdm1_data   ;
    wire                      sdm1_reset  ;
    wire                      sdm1_toggle ;
    wire [1:0]                sdm1_width  ;

    //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
    gt_common_gen gt_common_gen_inst (
        // Transceiver common block ports
        .gtrefclk00_in      (gtrefclk00         ),  // input         gtrefclk00_in       ,
        .gtrefclk01_in      (gtrefclk01         ),  // input         gtrefclk01_in       ,
        .qpll0reset_in      (qpll0reset         ),  // input         qpll0reset_in       ,
        .reset_all_in       (~s_axi_aresetn     ),  // input         reset_all_in        ,
        .freerun_clk_in     (fbclk              ),  // input         freerun_clk_in      ,
        .sdm1data_in        (sdm1_data          ),  // input  [24:0] sdm1data_in         ,
        .sdm1reset_in       (sdm1_reset         ),  // input         sdm1reset_in        ,
        .sdm1toggle_in      (sdm1_toggle        ),  // input         sdm1toggle_in       ,
        .sdm1width_in       (sdm1_width         ),  // input  [ 1:0] sdm1width_in        ,

        .txn_out            (txn_out            ),  // output [ 1:0] txn_out             ,
        .txp_out            (txp_out            ),  // output [ 1:0] txp_out             ,
        .qpll0lock_out      (qpll0lock_out      ),  // output        qpll0lock_out       ,
        .qpll0outclk_out    (qpll0outclk_out    ),  // output        qpll0outclk_out     ,
        .qpll0outrefclk_out (qpll0outrefclk_out ),  // output        qpll0outrefclk_out  ,

        .rxoutclk_out       (rxoutclk_out       ),  // output        rxoutclk_out        ,
        .txoutclk_out       (txoutclk_out       )   // output        txoutclk_out       ,
    );
    // INST_TAG_END ------ End INSTANTIATION Template ---------

    //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
    sdm_ctrl sdm_ctrl_inst (
        .fbclk              (fbclk              ),  // input   fbclk,
        .sys_clk            (sys_clk            ),  // input   sys_clk,
        .sdm1_data          (sdm1_data          ),  // output [24:0] sdm1_data,
        .sdm1_reset         (sdm1_reset         ),  // output  sdm1_reset,
        .sdm1_toggle        (sdm1_toggle        ),  // output  sdm1_toggle,
        .sdm1_width         (sdm1_width         ),  // output [ 1:0] sdm1_width,

        .up_rstn            (s_axi_aresetn      ),  // input   up_rstn,
        .up_clk             (s_axi_aclk         ),  // input   up_clk,
        .up_wreq            (up_wreq            ),  // input   up_wreq,
        .up_waddr           (up_waddr           ),  // input   [11:0] up_waddr,
        .up_wdata           (up_wdata           ),  // input   [31:0] up_wdata,
        .up_wack            (up_wack            ),  // output  up_wack,
        .up_rreq            (up_rreq            ),  // input   up_rreq,
        .up_raddr           (up_raddr           ),  // input   [11:0] up_raddr,
        .up_rdata           (up_rdata           ),  // output  [31:0] up_rdata,
        .up_rack            (up_rack            )   // output  up_rack;
    ); 
    // INST_TAG_END ------ End INSTANTIATION Template ---------

    // axi interface
    //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
    gt_common_sdm_up_axi #(
        .ADDRESS_WIDTH      (ADDRESS_WIDTH    ),
        .AXI_ADDRESS_WIDTH  (12               )) 
    gt_common_sdm_up_axi_inst (
        .up_rstn            (s_axi_aresetn    ),  // input   up_rstn,
        .up_clk             (s_axi_aclk       ),  // input   up_clk,

        .up_axi_awvalid     (s_axi_awvalid    ),  // input   up_axi_awvalid,
        .up_axi_awaddr      (s_axi_awaddr     ),  // input   [11:0] up_axi_awaddr,
        .up_axi_awready     (s_axi_awready    ),  // output  up_axi_awready,
        .up_axi_wvalid      (s_axi_wvalid     ),  // input   up_axi_wvalid,
        .up_axi_wdata       (s_axi_wdata      ),  // input   [31:0] up_axi_wdata,
        .up_axi_wstrb       (s_axi_wstrb      ),  // input   [3:0] up_axi_wstrb,
        .up_axi_wready      (s_axi_wready     ),  // output  up_axi_wready,
        .up_axi_bvalid      (s_axi_bvalid     ),  // output  up_axi_bvalid,
        .up_axi_bresp       (s_axi_bresp      ),  // output  [1:0] up_axi_bresp,
        .up_axi_bready      (s_axi_bready     ),  // input   up_axi_bready,
        .up_axi_arvalid     (s_axi_arvalid    ),  // input   up_axi_arvalid,
        .up_axi_araddr      (s_axi_araddr     ),  // input   [11:0] up_axi_araddr,
        .up_axi_arready     (s_axi_arready    ),  // output  up_axi_arready,
        .up_axi_rvalid      (s_axi_rvalid     ),  // output  up_axi_rvalid,
        .up_axi_rresp       (s_axi_rresp      ),  // output  [1:0] up_axi_rresp,
        .up_axi_rdata       (s_axi_rdata      ),  // output  [31:0] up_axi_rdata,
        .up_axi_rready      (s_axi_rready     ),  // input   up_axi_rready,

        .up_wreq            (up_wreq          ),  // output  up_wreq,
        .up_waddr           (up_waddr         ),  // output  [11:0] up_waddr,
        .up_wdata           (up_wdata         ),  // output  [31:0] up_wdata, 
        .up_wack            (up_wack          ),  // input   up_wack,
        .up_rreq            (up_rreq          ),  // output  up_rreq,
        .up_raddr           (up_raddr         ),  // output  [11:0] up_raddr,
        .up_rdata           (up_rdata         ),  // input   [31:0] up_rdata,
        .up_rack            (up_rack          )); // input   up_rack;
    // INST_TAG_END ------ End INSTANTIATION Template ---------

endmodule
